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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\TangPrimer-25K-example\UART\impl\gwsynthesis\uart_Hello.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\TangPrimer-25K-example\UART\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-3</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Aug 28 11:22:58 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>231</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>231</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>clk_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>100.000(MHz)</td>
<td>131.254(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>2.381</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_0_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.004</td>
<td>7.258</td>
</tr>
<tr>
<td>2</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_1_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>3</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_2_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>4</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_3_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>5</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_4_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>6</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_5_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>7</td>
<td>2.698</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_6_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.944</td>
</tr>
<tr>
<td>8</td>
<td>2.703</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_13_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.940</td>
</tr>
<tr>
<td>9</td>
<td>2.703</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_14_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.940</td>
</tr>
<tr>
<td>10</td>
<td>2.703</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_15_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.940</td>
</tr>
<tr>
<td>11</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_7_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>12</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_8_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>13</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_9_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>14</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_10_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>15</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_11_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>16</td>
<td>2.759</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_12_s0/RESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>6.893</td>
</tr>
<tr>
<td>17</td>
<td>3.191</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_valid_s0/SET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.028</td>
<td>6.480</td>
</tr>
<tr>
<td>18</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_1_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>19</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_2_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>20</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_3_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>21</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_4_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>22</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_5_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>23</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_6_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>24</td>
<td>3.264</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_7_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.468</td>
</tr>
<tr>
<td>25</td>
<td>3.462</td>
<td>uart_rx_inst/cycle_cnt_4_s0/Q</td>
<td>uart_rx_inst/rx_data_0_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.040</td>
<td>6.278</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.362</td>
<td>wait_cnt_21_s1/Q</td>
<td>wait_cnt_21_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>2</td>
<td>0.362</td>
<td>tx_cnt_0_s0/Q</td>
<td>tx_cnt_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>3</td>
<td>0.362</td>
<td>uart_tx_inst/cycle_cnt_0_s0/Q</td>
<td>uart_tx_inst/cycle_cnt_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>4</td>
<td>0.362</td>
<td>wait_cnt_4_s2/Q</td>
<td>wait_cnt_4_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>5</td>
<td>0.362</td>
<td>wait_cnt_6_s2/Q</td>
<td>wait_cnt_6_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>6</td>
<td>0.362</td>
<td>wait_cnt_5_s1/Q</td>
<td>wait_cnt_5_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>7</td>
<td>0.366</td>
<td>uart_rx_inst/bit_cnt_2_s0/Q</td>
<td>uart_rx_inst/bit_cnt_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>8</td>
<td>0.366</td>
<td>uart_rx_inst/state_1_s0/Q</td>
<td>uart_rx_inst/state_1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>9</td>
<td>0.366</td>
<td>wait_cnt_8_s1/Q</td>
<td>wait_cnt_8_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>10</td>
<td>0.366</td>
<td>wait_cnt_11_s1/Q</td>
<td>wait_cnt_11_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>11</td>
<td>0.366</td>
<td>wait_cnt_18_s1/Q</td>
<td>wait_cnt_18_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>12</td>
<td>0.370</td>
<td>uart_rx_inst/bit_cnt_1_s0/Q</td>
<td>uart_rx_inst/bit_cnt_1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.371</td>
</tr>
<tr>
<td>13</td>
<td>0.426</td>
<td>wait_cnt_0_s2/Q</td>
<td>wait_cnt_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.427</td>
</tr>
<tr>
<td>14</td>
<td>0.426</td>
<td>wait_cnt_17_s1/Q</td>
<td>wait_cnt_17_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.427</td>
</tr>
<tr>
<td>15</td>
<td>0.442</td>
<td>wait_cnt_9_s1/Q</td>
<td>wait_cnt_9_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.443</td>
</tr>
<tr>
<td>16</td>
<td>0.442</td>
<td>wait_cnt_20_s1/Q</td>
<td>wait_cnt_20_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.443</td>
</tr>
<tr>
<td>17</td>
<td>0.448</td>
<td>wait_cnt_7_s1/Q</td>
<td>wait_cnt_7_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.449</td>
</tr>
<tr>
<td>18</td>
<td>0.448</td>
<td>uart_rx_inst/rx_d0_s0/Q</td>
<td>uart_rx_inst/rx_d1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.449</td>
</tr>
<tr>
<td>19</td>
<td>0.460</td>
<td>wait_cnt_13_s2/Q</td>
<td>wait_cnt_14_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.461</td>
</tr>
<tr>
<td>20</td>
<td>0.460</td>
<td>wait_cnt_31_s1/Q</td>
<td>wait_cnt_31_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.437</td>
</tr>
<tr>
<td>21</td>
<td>0.466</td>
<td>uart_rx_inst/state_2_s1/Q</td>
<td>uart_rx_inst/state_2_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.467</td>
</tr>
<tr>
<td>22</td>
<td>0.473</td>
<td>uart_rx_inst/rx_data_1_s0/Q</td>
<td>tx_data_1_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.005</td>
<td>0.469</td>
</tr>
<tr>
<td>23</td>
<td>0.476</td>
<td>uart_rx_inst/cycle_cnt_0_s0/Q</td>
<td>uart_rx_inst/cycle_cnt_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>24</td>
<td>0.476</td>
<td>wait_cnt_1_s2/Q</td>
<td>wait_cnt_1_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>25</td>
<td>0.476</td>
<td>wait_cnt_27_s1/Q</td>
<td>wait_cnt_27_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>10000000000.000</td>
<td>4.828</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>state_0_s0</td>
</tr>
<tr>
<td>2</td>
<td>10000000000.000</td>
<td>4.815</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>tx_cnt_3_s0</td>
</tr>
<tr>
<td>3</td>
<td>10000000000.000</td>
<td>4.815</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>tx_cnt_1_s0</td>
</tr>
<tr>
<td>4</td>
<td>10000000000.000</td>
<td>4.815</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>wait_cnt_27_s1</td>
</tr>
<tr>
<td>5</td>
<td>10000000000.000</td>
<td>4.828</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>wait_cnt_18_s1</td>
</tr>
<tr>
<td>6</td>
<td>10000000000.000</td>
<td>4.815</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>tx_data_2_s2</td>
</tr>
<tr>
<td>7</td>
<td>10000000000.000</td>
<td>4.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>uart_rx_inst/cycle_cnt_13_s0</td>
</tr>
<tr>
<td>8</td>
<td>10000000000.000</td>
<td>4.822</td>
<td>-10000000000.000</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>uart_tx_inst/state_2_s1</td>
</tr>
<tr>
<td>9</td>
<td>10000000000.000</td>
<td>4.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>uart_tx_inst/state_2_s1</td>
</tr>
<tr>
<td>10</td>
<td>10000000000.000</td>
<td>4.822</td>
<td>-10000000000.000</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>uart_tx_inst/tx_reg_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.381</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.661</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>8.280</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_0_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.019</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>10.661</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.004</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 37.318%; route: 4.182, 57.622%; tC2Q: 0.367, 5.060%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 67.010%; route: 0.336, 32.990%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_1_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>uart_rx_inst/cycle_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>uart_rx_inst/cycle_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_2_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][B]</td>
<td>uart_rx_inst/cycle_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[0][B]</td>
<td>uart_rx_inst/cycle_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_3_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][A]</td>
<td>uart_rx_inst/cycle_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[1][A]</td>
<td>uart_rx_inst/cycle_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_5_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[2][A]</td>
<td>uart_rx_inst/cycle_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[2][A]</td>
<td>uart_rx_inst/cycle_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.698</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.966</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.715</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[2][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_6_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[2][B]</td>
<td>uart_rx_inst/cycle_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C48[2][B]</td>
<td>uart_rx_inst/cycle_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.001%; route: 3.869, 55.711%; tC2Q: 0.367, 5.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.703</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.962</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.962</td>
<td>0.710</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_13_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>uart_rx_inst/cycle_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>uart_rx_inst/cycle_cnt_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.028%; route: 3.864, 55.680%; tC2Q: 0.367, 5.291%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.703</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.962</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.962</td>
<td>0.710</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_14_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>uart_rx_inst/cycle_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>uart_rx_inst/cycle_cnt_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.028%; route: 3.864, 55.680%; tC2Q: 0.367, 5.291%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.703</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.962</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.665</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.962</td>
<td>0.710</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_15_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>uart_rx_inst/cycle_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>10.665</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>uart_rx_inst/cycle_cnt_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.028%; route: 3.864, 55.680%; tC2Q: 0.367, 5.291%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_7_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[0][A]</td>
<td>uart_rx_inst/cycle_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[0][A]</td>
<td>uart_rx_inst/cycle_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[0][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_8_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[0][B]</td>
<td>uart_rx_inst/cycle_cnt_8_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[0][B]</td>
<td>uart_rx_inst/cycle_cnt_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_9_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[1][A]</td>
<td>uart_rx_inst/cycle_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[1][A]</td>
<td>uart_rx_inst/cycle_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_10_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[1][B]</td>
<td>uart_rx_inst/cycle_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[1][B]</td>
<td>uart_rx_inst/cycle_cnt_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_11_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[2][A]</td>
<td>uart_rx_inst/cycle_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[2][A]</td>
<td>uart_rx_inst/cycle_cnt_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.759</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.915</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.808</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][B]</td>
<td>uart_rx_inst/n135_s0/I2</td>
</tr>
<tr>
<td>7.251</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>16</td>
<td>R20C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n135_s0/F</td>
</tr>
<tr>
<td>7.915</td>
<td>0.664</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[2][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_12_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.031</td>
<td>0.349</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C49[2][B]</td>
<td>uart_rx_inst/cycle_cnt_12_s0/CLK</td>
</tr>
<tr>
<td>10.674</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C49[2][B]</td>
<td>uart_rx_inst/cycle_cnt_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.708, 39.293%; route: 3.817, 55.380%; tC2Q: 0.367, 5.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.191%; route: 0.349, 33.809%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.502</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_valid_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.502</td>
<td>0.343</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_valid_s0/SET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.050</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[0][A]</td>
<td>uart_rx_inst/rx_data_valid_s0/CLK</td>
</tr>
<tr>
<td>10.693</td>
<td>-0.358</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C48[0][A]</td>
<td>uart_rx_inst/rx_data_valid_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.028</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.611%; route: 3.352, 51.722%; tC2Q: 0.367, 5.667%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.981%; route: 0.368, 35.019%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][A]</td>
<td>uart_rx_inst/rx_data_1_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[1][A]</td>
<td>uart_rx_inst/rx_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][B]</td>
<td>uart_rx_inst/rx_data_2_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[1][B]</td>
<td>uart_rx_inst/rx_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>uart_rx_inst/rx_data_3_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>uart_rx_inst/rx_data_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>uart_rx_inst/rx_data_4_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>uart_rx_inst/rx_data_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[3][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[3][A]</td>
<td>uart_rx_inst/rx_data_5_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[3][A]</td>
<td>uart_rx_inst/rx_data_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[3][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[3][B]</td>
<td>uart_rx_inst/rx_data_6_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[3][B]</td>
<td>uart_rx_inst/rx_data_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.264</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.331</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][B]</td>
<td>uart_rx_inst/rx_data_7_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[0][B]</td>
<td>uart_rx_inst/rx_data_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 42.690%; route: 3.340, 51.633%; tC2Q: 0.367, 5.677%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.462</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.300</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.763</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.581</td>
<td>0.192</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[3][A]</td>
<td>uart_rx_inst/n25_s6/I1</td>
</tr>
<tr>
<td>2.059</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C48[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s6/F</td>
</tr>
<tr>
<td>2.216</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][A]</td>
<td>uart_rx_inst/n25_s4/I1</td>
</tr>
<tr>
<td>2.721</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n25_s4/F</td>
</tr>
<tr>
<td>3.433</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[3][B]</td>
<td>uart_rx_inst/next_state_1_s20/I2</td>
</tr>
<tr>
<td>3.831</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C49[3][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s20/F</td>
</tr>
<tr>
<td>4.676</td>
<td>0.845</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[3][A]</td>
<td>uart_rx_inst/next_state_0_s12/I0</td>
</tr>
<tr>
<td>4.931</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R18C50[3][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_0_s12/F</td>
</tr>
<tr>
<td>5.787</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td>uart_rx_inst/n55_s0/I0</td>
</tr>
<tr>
<td>6.321</td>
<td>0.534</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n55_s0/COUT</td>
</tr>
<tr>
<td>6.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td>uart_rx_inst/n56_s0/CIN</td>
</tr>
<tr>
<td>6.369</td>
<td>0.048</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C49[0][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n56_s0/COUT</td>
</tr>
<tr>
<td>6.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[1][A]</td>
<td>uart_rx_inst/n57_s0/CIN</td>
</tr>
<tr>
<td>6.417</td>
<td>0.048</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n57_s0/COUT</td>
</tr>
<tr>
<td>6.663</td>
<td>0.246</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C49[2][B]</td>
<td>uart_rx_inst/n76_s2/I0</td>
</tr>
<tr>
<td>7.159</td>
<td>0.496</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R21C49[2][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n76_s2/F</td>
</tr>
<tr>
<td>7.300</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.062</td>
<td>0.379</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C49[2][A]</td>
<td>uart_rx_inst/rx_data_0_s0/CLK</td>
</tr>
<tr>
<td>10.763</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C49[2][A]</td>
<td>uart_rx_inst/rx_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.040</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.761, 43.979%; route: 3.150, 50.172%; tC2Q: 0.367, 5.849%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.284%; route: 0.379, 35.716%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.239</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.877</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_21_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_21_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>wait_cnt_21_s1/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R20C45[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_21_s1/Q</td>
</tr>
<tr>
<td>1.056</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>n144_s5/I2</td>
</tr>
<tr>
<td>1.239</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td style=" background: #97FFFF;">n144_s5/F</td>
</tr>
<tr>
<td>1.239</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_21_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>wait_cnt_21_s1/CLK</td>
</tr>
<tr>
<td>0.877</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>wait_cnt_21_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.225</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.863</td>
</tr>
<tr>
<td class="label">From</td>
<td>tx_cnt_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>tx_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[0][A]</td>
<td>tx_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.035</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R22C47[0][A]</td>
<td style=" font-weight:bold;">tx_cnt_0_s0/Q</td>
</tr>
<tr>
<td>1.042</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[0][A]</td>
<td>n33_s3/I0</td>
</tr>
<tr>
<td>1.225</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C47[0][A]</td>
<td style=" background: #97FFFF;">n33_s3/F</td>
</tr>
<tr>
<td>1.225</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C47[0][A]</td>
<td style=" font-weight:bold;">tx_cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[0][A]</td>
<td>tx_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>0.863</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C47[0][A]</td>
<td>tx_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.207</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_tx_inst/cycle_cnt_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_tx_inst/cycle_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>uart_tx_inst/cycle_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.016</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">uart_tx_inst/cycle_cnt_0_s0/Q</td>
</tr>
<tr>
<td>1.023</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>uart_tx_inst/n159_s2/I0</td>
</tr>
<tr>
<td>1.207</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" background: #97FFFF;">uart_tx_inst/n159_s2/F</td>
</tr>
<tr>
<td>1.207</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">uart_tx_inst/cycle_cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>uart_tx_inst/cycle_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>0.844</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>uart_tx_inst/cycle_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.228</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.866</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_4_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.864</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C44[0][A]</td>
<td>wait_cnt_4_s2/CLK</td>
</tr>
<tr>
<td>1.037</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R23C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_4_s2/Q</td>
</tr>
<tr>
<td>1.044</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C44[0][A]</td>
<td>n178_s7/I2</td>
</tr>
<tr>
<td>1.228</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C44[0][A]</td>
<td style=" background: #97FFFF;">n178_s7/F</td>
</tr>
<tr>
<td>1.228</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_4_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.864</td>
<td>0.189</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C44[0][A]</td>
<td>wait_cnt_4_s2/CLK</td>
</tr>
<tr>
<td>0.866</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C44[0][A]</td>
<td>wait_cnt_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.138%; route: 0.189, 21.862%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.138%; route: 0.189, 21.862%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.230</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.868</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_6_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_6_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.867</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C44[0][A]</td>
<td>wait_cnt_6_s2/CLK</td>
</tr>
<tr>
<td>1.039</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R22C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_6_s2/Q</td>
</tr>
<tr>
<td>1.047</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C44[0][A]</td>
<td>n174_s7/I2</td>
</tr>
<tr>
<td>1.230</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C44[0][A]</td>
<td style=" background: #97FFFF;">n174_s7/F</td>
</tr>
<tr>
<td>1.230</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_6_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.867</td>
<td>0.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C44[0][A]</td>
<td>wait_cnt_6_s2/CLK</td>
</tr>
<tr>
<td>0.868</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C44[0][A]</td>
<td>wait_cnt_6_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.948%; route: 0.191, 22.052%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.948%; route: 0.191, 22.052%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.232</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.870</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>wait_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>1.041</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_5_s1/Q</td>
</tr>
<tr>
<td>1.049</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>n176_s5/I2</td>
</tr>
<tr>
<td>1.232</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td style=" background: #97FFFF;">n176_s5/F</td>
</tr>
<tr>
<td>1.232</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_5_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>wait_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>0.870</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C44[0][A]</td>
<td>wait_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.243</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.877</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/bit_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/bit_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][A]</td>
<td>uart_rx_inst/bit_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R20C49[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/bit_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.059</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][A]</td>
<td>uart_rx_inst/n106_s1/I0</td>
</tr>
<tr>
<td>1.243</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C49[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n106_s1/F</td>
</tr>
<tr>
<td>1.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C49[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/bit_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][A]</td>
<td>uart_rx_inst/bit_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>0.877</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C49[1][A]</td>
<td>uart_rx_inst/bit_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.238</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/state_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/state_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][A]</td>
<td>uart_rx_inst/state_1_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>11</td>
<td>R20C50[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/state_1_s0/Q</td>
</tr>
<tr>
<td>1.054</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][A]</td>
<td>uart_rx_inst/next_state_1_s13/I2</td>
</tr>
<tr>
<td>1.238</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C50[1][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_1_s13/F</td>
</tr>
<tr>
<td>1.238</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/state_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][A]</td>
<td>uart_rx_inst/state_1_s0/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C50[1][A]</td>
<td>uart_rx_inst/state_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.231</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_8_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.864</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>wait_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>1.037</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R21C43[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_8_s1/Q</td>
</tr>
<tr>
<td>1.048</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>n170_s6/I0</td>
</tr>
<tr>
<td>1.231</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" background: #97FFFF;">n170_s6/F</td>
</tr>
<tr>
<td>1.231</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_8_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.864</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>wait_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>0.865</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>wait_cnt_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.192%; route: 0.188, 21.808%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.192%; route: 0.188, 21.808%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.229</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.863</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_11_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_11_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[1][A]</td>
<td>wait_cnt_11_s1/CLK</td>
</tr>
<tr>
<td>1.035</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R22C43[1][A]</td>
<td style=" font-weight:bold;">wait_cnt_11_s1/Q</td>
</tr>
<tr>
<td>1.045</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[1][A]</td>
<td>n164_s5/I2</td>
</tr>
<tr>
<td>1.229</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C43[1][A]</td>
<td style=" background: #97FFFF;">n164_s5/F</td>
</tr>
<tr>
<td>1.229</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C43[1][A]</td>
<td style=" font-weight:bold;">wait_cnt_11_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[1][A]</td>
<td>wait_cnt_11_s1/CLK</td>
</tr>
<tr>
<td>0.863</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C43[1][A]</td>
<td>wait_cnt_11_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.227</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.861</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_18_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_18_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[0][A]</td>
<td>wait_cnt_18_s1/CLK</td>
</tr>
<tr>
<td>1.033</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R23C43[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_18_s1/Q</td>
</tr>
<tr>
<td>1.043</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[0][A]</td>
<td>n150_s5/I2</td>
</tr>
<tr>
<td>1.227</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C43[0][A]</td>
<td style=" background: #97FFFF;">n150_s5/F</td>
</tr>
<tr>
<td>1.227</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C43[0][A]</td>
<td style=" font-weight:bold;">wait_cnt_18_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[0][A]</td>
<td>wait_cnt_18_s1/CLK</td>
</tr>
<tr>
<td>0.861</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C43[0][A]</td>
<td>wait_cnt_18_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.246</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.877</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/bit_cnt_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/bit_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][A]</td>
<td>uart_rx_inst/bit_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>11</td>
<td>R20C49[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/bit_cnt_1_s0/Q</td>
</tr>
<tr>
<td>1.063</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][A]</td>
<td>uart_rx_inst/n107_s0/I1</td>
</tr>
<tr>
<td>1.246</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C49[0][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n107_s0/F</td>
</tr>
<tr>
<td>1.246</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C49[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/bit_cnt_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[0][A]</td>
<td>uart_rx_inst/bit_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>0.877</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C49[0][A]</td>
<td>uart_rx_inst/bit_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 49.515%; route: 0.014, 3.883%; tC2Q: 0.173, 46.602%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.426</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.289</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.863</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[2][A]</td>
<td>wait_cnt_0_s2/CLK</td>
</tr>
<tr>
<td>1.035</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R22C47[2][A]</td>
<td style=" font-weight:bold;">wait_cnt_0_s2/Q</td>
</tr>
<tr>
<td>1.042</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[2][A]</td>
<td>n186_s7/I2</td>
</tr>
<tr>
<td>1.289</td>
<td>0.247</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C47[2][A]</td>
<td style=" background: #97FFFF;">n186_s7/F</td>
</tr>
<tr>
<td>1.289</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C47[2][A]</td>
<td style=" font-weight:bold;">wait_cnt_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C47[2][A]</td>
<td>wait_cnt_0_s2/CLK</td>
</tr>
<tr>
<td>0.863</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C47[2][A]</td>
<td>wait_cnt_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.247, 57.865%; route: 0.007, 1.685%; tC2Q: 0.173, 40.449%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.426</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.287</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.861</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_17_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_17_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[2][A]</td>
<td>wait_cnt_17_s1/CLK</td>
</tr>
<tr>
<td>1.033</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R23C43[2][A]</td>
<td style=" font-weight:bold;">wait_cnt_17_s1/Q</td>
</tr>
<tr>
<td>1.040</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[2][A]</td>
<td>n152_s5/I2</td>
</tr>
<tr>
<td>1.287</td>
<td>0.247</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C43[2][A]</td>
<td style=" background: #97FFFF;">n152_s5/F</td>
</tr>
<tr>
<td>1.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C43[2][A]</td>
<td style=" font-weight:bold;">wait_cnt_17_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[2][A]</td>
<td>wait_cnt_17_s1/CLK</td>
</tr>
<tr>
<td>0.861</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C43[2][A]</td>
<td>wait_cnt_17_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.247, 57.865%; route: 0.007, 1.685%; tC2Q: 0.173, 40.449%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.442</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.861</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_9_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[0][B]</td>
<td>wait_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R23C43[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_9_s1/Q</td>
</tr>
<tr>
<td>1.119</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C43[0][B]</td>
<td>n168_s5/I2</td>
</tr>
<tr>
<td>1.303</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C43[0][B]</td>
<td style=" background: #97FFFF;">n168_s5/F</td>
</tr>
<tr>
<td>1.303</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C43[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_9_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C43[0][B]</td>
<td>wait_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>0.861</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C43[0][B]</td>
<td>wait_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 41.463%; route: 0.090, 20.325%; tC2Q: 0.169, 38.211%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.574%; route: 0.184, 21.426%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.442</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.316</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.875</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_20_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_20_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>wait_cnt_20_s1/CLK</td>
</tr>
<tr>
<td>1.043</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R21C45[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_20_s1/Q</td>
</tr>
<tr>
<td>1.133</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>n146_s5/I2</td>
</tr>
<tr>
<td>1.316</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" background: #97FFFF;">n146_s5/F</td>
</tr>
<tr>
<td>1.316</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_20_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>wait_cnt_20_s1/CLK</td>
</tr>
<tr>
<td>0.875</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[0][B]</td>
<td>wait_cnt_20_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 41.463%; route: 0.090, 20.325%; tC2Q: 0.169, 38.211%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.311</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.863</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>wait_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>1.031</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R22C43[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_7_s1/Q</td>
</tr>
<tr>
<td>1.127</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>n172_s5/I2</td>
</tr>
<tr>
<td>1.311</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td style=" background: #97FFFF;">n172_s5/F</td>
</tr>
<tr>
<td>1.311</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_7_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>wait_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>0.863</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>wait_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 40.909%; route: 0.096, 21.390%; tC2Q: 0.169, 37.701%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.290</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/rx_d0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/rx_d1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td>uart_rx_inst/rx_d0_s0/CLK</td>
</tr>
<tr>
<td>1.011</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C48[0][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_d0_s0/Q</td>
</tr>
<tr>
<td>1.290</td>
<td>0.280</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C48[0][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_d1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[0][A]</td>
<td>uart_rx_inst/rx_d1_s0/CLK</td>
</tr>
<tr>
<td>0.843</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C48[0][A]</td>
<td>uart_rx_inst/rx_d1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.280, 62.299%; tC2Q: 0.169, 37.701%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.460</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.334</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.875</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_13_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_14_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[2][B]</td>
<td>wait_cnt_13_s2/CLK</td>
</tr>
<tr>
<td>1.043</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R21C45[2][B]</td>
<td style=" font-weight:bold;">wait_cnt_13_s2/Q</td>
</tr>
<tr>
<td>1.151</td>
<td>0.108</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>n158_s5/I0</td>
</tr>
<tr>
<td>1.334</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" background: #97FFFF;">n158_s5/F</td>
</tr>
<tr>
<td>1.334</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td style=" font-weight:bold;">wait_cnt_14_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>wait_cnt_14_s1/CLK</td>
</tr>
<tr>
<td>0.875</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C45[1][B]</td>
<td>wait_cnt_14_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 39.844%; route: 0.108, 23.438%; tC2Q: 0.169, 36.719%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.460</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.306</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_31_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_31_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.194</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C45[3][A]</td>
<td>wait_cnt_31_s1/CLK</td>
</tr>
<tr>
<td>1.039</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R23C45[3][A]</td>
<td style=" font-weight:bold;">wait_cnt_31_s1/Q</td>
</tr>
<tr>
<td>1.129</td>
<td>0.090</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C45[3][A]</td>
<td>n124_s5/I2</td>
</tr>
<tr>
<td>1.306</td>
<td>0.178</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R23C45[3][A]</td>
<td style=" background: #97FFFF;">n124_s5/F</td>
</tr>
<tr>
<td>1.306</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C45[3][A]</td>
<td style=" font-weight:bold;">wait_cnt_31_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.194</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C45[3][A]</td>
<td>wait_cnt_31_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>-0.023</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C45[3][A]</td>
<td>wait_cnt_31_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.706%; route: 0.194, 22.294%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.178, 40.659%; route: 0.090, 20.604%; tC2Q: 0.169, 38.736%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.706%; route: 0.194, 22.294%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.466</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.338</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/state_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[2][A]</td>
<td>uart_rx_inst/state_2_s1/CLK</td>
</tr>
<tr>
<td>1.040</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R20C50[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/state_2_s1/Q</td>
</tr>
<tr>
<td>1.154</td>
<td>0.114</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[2][A]</td>
<td>uart_rx_inst/next_state_2_s14/I1</td>
</tr>
<tr>
<td>1.338</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C50[2][A]</td>
<td style=" background: #97FFFF;">uart_rx_inst/next_state_2_s14/F</td>
</tr>
<tr>
<td>1.338</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[2][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/state_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[2][A]</td>
<td>uart_rx_inst/state_2_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C50[2][A]</td>
<td>uart_rx_inst/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 39.332%; route: 0.114, 24.422%; tC2Q: 0.169, 36.247%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.473</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.338</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/rx_data_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>tx_data_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][A]</td>
<td>uart_rx_inst/rx_data_1_s0/CLK</td>
</tr>
<tr>
<td>1.041</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R21C48[1][A]</td>
<td style=" font-weight:bold;">uart_rx_inst/rx_data_1_s0/Q</td>
</tr>
<tr>
<td>1.154</td>
<td>0.113</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C47[1][A]</td>
<td>n200_s12/I2</td>
</tr>
<tr>
<td>1.338</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C47[1][A]</td>
<td style=" background: #97FFFF;">n200_s12/F</td>
</tr>
<tr>
<td>1.338</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C47[1][A]</td>
<td style=" font-weight:bold;">tx_data_1_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.864</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C47[1][A]</td>
<td>tx_data_1_s2/CLK</td>
</tr>
<tr>
<td>0.865</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C47[1][A]</td>
<td>tx_data_1_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.005</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 39.130%; route: 0.113, 24.041%; tC2Q: 0.173, 36.829%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.192%; route: 0.188, 21.808%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.319</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_rx_inst/cycle_cnt_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_rx_inst/cycle_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.014</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R16C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_0_s0/Q</td>
</tr>
<tr>
<td>1.021</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/n152_s2/I0</td>
</tr>
<tr>
<td>1.319</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td style=" background: #97FFFF;">uart_rx_inst/n152_s2/F</td>
</tr>
<tr>
<td>1.319</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td style=" font-weight:bold;">uart_rx_inst/cycle_cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>0.843</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>uart_rx_inst/cycle_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.351</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.875</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_1_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C46[1][B]</td>
<td>wait_cnt_1_s2/CLK</td>
</tr>
<tr>
<td>1.046</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R23C46[1][B]</td>
<td style=" font-weight:bold;">wait_cnt_1_s2/Q</td>
</tr>
<tr>
<td>1.053</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C46[1][B]</td>
<td>n184_s7/I2</td>
</tr>
<tr>
<td>1.351</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C46[1][B]</td>
<td style=" background: #97FFFF;">n184_s7/F</td>
</tr>
<tr>
<td>1.351</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C46[1][B]</td>
<td style=" font-weight:bold;">wait_cnt_1_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.873</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C46[1][B]</td>
<td>wait_cnt_1_s2/CLK</td>
</tr>
<tr>
<td>0.875</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C46[1][B]</td>
<td>wait_cnt_1_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.333%; route: 0.198, 22.667%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.353</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.877</td>
</tr>
<tr>
<td class="label">From</td>
<td>wait_cnt_27_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>wait_cnt_27_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C46[0][B]</td>
<td>wait_cnt_27_s1/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R22C46[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_27_s1/Q</td>
</tr>
<tr>
<td>1.056</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C46[0][B]</td>
<td>n132_s5/I2</td>
</tr>
<tr>
<td>1.353</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C46[0][B]</td>
<td style=" background: #97FFFF;">n132_s5/F</td>
</tr>
<tr>
<td>1.353</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C46[0][B]</td>
<td style=" font-weight:bold;">wait_cnt_27_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>121</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C46[0][B]</td>
<td>wait_cnt_27_s1/CLK</td>
</tr>
<tr>
<td>0.877</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C46[0][B]</td>
<td>wait_cnt_27_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.828</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>state_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.044</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>state_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.872</td>
<td>0.194</td>
<td>tNET</td>
<td>FF</td>
<td>state_0_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>tx_cnt_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.073</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>tx_cnt_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.888</td>
<td>0.211</td>
<td>tNET</td>
<td>FF</td>
<td>tx_cnt_3_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>tx_cnt_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.073</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>tx_cnt_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.888</td>
<td>0.211</td>
<td>tNET</td>
<td>FF</td>
<td>tx_cnt_1_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>wait_cnt_27_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.068</td>
<td>0.386</td>
<td>tNET</td>
<td>RR</td>
<td>wait_cnt_27_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.883</td>
<td>0.206</td>
<td>tNET</td>
<td>FF</td>
<td>wait_cnt_27_s1/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.828</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>wait_cnt_18_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.039</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>wait_cnt_18_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.867</td>
<td>0.190</td>
<td>tNET</td>
<td>FF</td>
<td>wait_cnt_18_s1/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>tx_data_2_s2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.071</td>
<td>0.388</td>
<td>tNET</td>
<td>RR</td>
<td>tx_data_2_s2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.886</td>
<td>0.208</td>
<td>tNET</td>
<td>FF</td>
<td>tx_data_2_s2/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>uart_rx_inst/cycle_cnt_13_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>uart_rx_inst/cycle_cnt_13_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.851</td>
<td>0.173</td>
<td>tNET</td>
<td>FF</td>
<td>uart_rx_inst/cycle_cnt_13_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.822</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>uart_tx_inst/state_2_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>6.021</td>
<td>0.333</td>
<td>tNET</td>
<td>FF</td>
<td>uart_tx_inst/state_2_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>uart_tx_inst/state_2_s1/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>uart_tx_inst/state_2_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.020</td>
<td>0.338</td>
<td>tNET</td>
<td>RR</td>
<td>uart_tx_inst/state_2_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.849</td>
<td>0.172</td>
<td>tNET</td>
<td>FF</td>
<td>uart_tx_inst/state_2_s1/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.822</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>uart_tx_inst/tx_reg_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>6.024</td>
<td>0.337</td>
<td>tNET</td>
<td>FF</td>
<td>uart_tx_inst/tx_reg_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.846</td>
<td>0.170</td>
<td>tNET</td>
<td>RR</td>
<td>uart_tx_inst/tx_reg_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>121</td>
<td>clk_d</td>
<td>2.381</td>
<td>0.391</td>
</tr>
<tr>
<td>46</td>
<td>n126_12</td>
<td>5.854</td>
<td>1.416</td>
</tr>
<tr>
<td>23</td>
<td>tx_cnt_7_11</td>
<td>6.025</td>
<td>1.379</td>
</tr>
<tr>
<td>22</td>
<td>n126_29</td>
<td>6.025</td>
<td>0.550</td>
</tr>
<tr>
<td>16</td>
<td>n135_3</td>
<td>2.381</td>
<td>1.028</td>
</tr>
<tr>
<td>16</td>
<td>n142_3</td>
<td>4.409</td>
<td>0.667</td>
</tr>
<tr>
<td>12</td>
<td>state[2]</td>
<td>3.120</td>
<td>1.085</td>
</tr>
<tr>
<td>12</td>
<td>bit_cnt[0]</td>
<td>3.679</td>
<td>0.574</td>
</tr>
<tr>
<td>11</td>
<td>state[1]</td>
<td>3.062</td>
<td>1.090</td>
</tr>
<tr>
<td>11</td>
<td>bit_cnt[1]</td>
<td>3.623</td>
<td>0.380</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R18C49</td>
<td>41.67%</td>
</tr>
<tr>
<td>R20C47</td>
<td>31.94%</td>
</tr>
<tr>
<td>R18C48</td>
<td>31.94%</td>
</tr>
<tr>
<td>R22C44</td>
<td>30.56%</td>
</tr>
<tr>
<td>R22C43</td>
<td>29.17%</td>
</tr>
<tr>
<td>R20C49</td>
<td>29.17%</td>
</tr>
<tr>
<td>R22C46</td>
<td>27.78%</td>
</tr>
<tr>
<td>R23C44</td>
<td>26.39%</td>
</tr>
<tr>
<td>R22C45</td>
<td>26.39%</td>
</tr>
<tr>
<td>R20C46</td>
<td>25.00%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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